\begin{abstract}
Three-dimensional (3D) circuit integration is a promising technology to
alleviate performance and power related issues raised by interconnects in
nanometer CMOS. Physical planning of three-dimensional integrated circuits is
substantially different from that of traditional planar integrated circuits,
due to the presence of multiple layers of dies. To realize the full potential
offered by three-dimensional integration, it is necessary to take physical
information into consideration at higher-levels of the design abstraction for
3D ICs. This paper proposes an incremental system-level synthesis framework
that tightly integrates behavioral synthesis of modules into the layer
assignment and floorplanning stage of 3D IC design. Behavioral synthesis is
implemented as a sub-routine to be called to adjust
delay/power/variability/area of circuit modules during the physical planning
process. Experimental results show that with the proposed
\emph{synthesis-during-planning} methodology, the overall timing yield is
improved by 8\%, and the chip peak temperature reduced by 6.6
$^{\tiny\textrm{o}}$C, compared to the conventional
\emph{planning-after-synthesis} approach.
\end{abstract}
\vspace{10pt}

\section{Introduction}\label{sec:intro}

To further improve integration density and to tackle the interconnect challenge
as technology continues scaling, researchers have been pushing forward
three-dimensional (3D) IC stacking~\cite{Davis2005,Xie2006}. In a 3D IC,
multiple device layers are stacked together with direct vertical interconnects
through substrates. 3D ICs offer a number of advantages over traditional
two-dimensional (2D) design, such as (1) higher packing density and smaller
footprint; (2) shorter global interconnect due to the short length of
through-silicon vias (TSVs) and the flexibility of vertical routing, leading to
higher performance and lower power consumption of interconnects; (3) support of
heterogenous integration: each single die can have different technologies.

As we pack more and more transistors into a single chip, the pace of
productivity gains has not kept up to address the increases in design
complexity. Consequently, we have seen a recent trend of moving design
abstraction to a higher level, with an emphasis on \textbf{Electronic System
Level (ESL)} design methodologies. A very important component of ESL is raising
the level of abstraction of hardware design. High-level synthesis (HLS)
provides this component by providing automation to generate optimized hardware
from a high-level description of the function or algorithm to be implemented in
hardware. HLS generates a cycle-accurate specification at the register-transfer
level (RTL) that is then used in existing ASIC or FPGA design methodologies.
%Commercial high-level synthesis tools~\cite{HLS:newbook} have recently gained a
%lot of attention as evidenced in recent conference HLS workshops (DATE2008,
%DAC2008, ASPDAC2009), conference panels and publications that track the
%industry.

Conventional thinking on HLS for 3D ICs focused on such a
\emph{planning-after-synthesis} flow that HLS was done first to generate the
block-level (function unit) implementation of circuits, and 3D integration is
used to put together blocks such as adders and multipliers. For any
unsatisfactory in the integration, HLS is redone and then physical design
follows. The problem here is that these blocks might be very small in size and
this leads to a fine granularity in 3D integration. The physical planning
(layer assignment and floorplanning) at this granularity might be impractical
in real designs for the following reasons: (1) Very fine-grain integration of
3D ICs splits modules to different layers and creates more inter-layer
connections, which is not desirable as the delay and area overheads on
through-silicon vias (TSVs) is not negligible. (2)In typical designs there
would be thousands of such function-level blocks. Optimal physical planning for
such a input scale could be challenging and time-consuming, which complicates
the early-stage design exploration and increase time to market of a design.

A new thinking is to bring 3D integration to a higher level, to address the
integration of modules in a system, instead of function units inside a module.
In this way, the combination of HLS and 3D IC design might be a different
story. HLS is implemented as a sub-routine to be called to adjust
delay/power/area of circuit modules during the physical planning process. In
this \emph{synthesis-during-planning} flow, HLS is first performed to estimate
the delay, power and area of architectural modules in the system, such as ALU,
FPU, \emph{etc}. Then 3D partition and floorplanning are done to integrate
these modules, and timing/power/variability/thermal analysis are performed on
the planned results. If the constrains are not met, the modules on critical
paths or hot spots are picked out and sent back to HLS. In this iteration, HLS
is to re-explore the design space of such modules on certain directions and to
generate new implementations with different (delay, power, variability, area)
properties. Modules with new internal architectures provide new opportunities
for the 3D integration and therefore it's likely to improve the design towards
the constraints. With multiple iterations it will generate designs that are
ready for low-level implementation. This flow can avoid the problem and
concerns on very fine-granularity 3D integration, and can be done quickly to
get a reasonable 3D implementation in the early stage of a design process.
\vspace{10pt}
